Abstract
Software performance in terms of clock cycles can be measured on the hardware platform. However, the availability of hardware platform is critical in early stages of the design flow. One possible solution is to implement the hardware components at cycle-accurate level such that the performance estimation is given by the micro-architectural simulation in number of cycles. But the design space exploration at this level may require huge simulation time. This article presents a cycle-accurate performance estimation methodology with reduced simulation time. The simulation results are computed and stored in a performance estimation database. The results are used for mapping application functions on architecture components. We estimate the application performance as a linear combination of function performances on mapped components. The proposed approach decreases the overall simulation time while maintaining the accuracy in terms of clock cycles. We have evaluated the design with H.264 application and found that it reduces 50 % of the simulation time.