Abstract
The High Efficiency Video Coding (HEVC) is a proposal of new video coding standard that will be used for a wide range of applications like ULTRA HD and 3D applications. The Moving Picture Expert Group (MPEG) and the Video Coding Expert Group (VCEG) have established a Joint Collaborative Team on Video Coding (JCT-VC) to develop the HEVC standard which is expected to provide a significant improvement in data transmission and streaming efficiency compared to H.264/AVC (Advanced Video Coding). In this proposal standard, various modules of coding are defined. Among the most complex is the module of the intra prediction. The HEVC defines 35 modes of intra prediction for 8x8, 16x16, 32x32, 3 modes for 64x64 and 17 modes for 4x4 while the H. 264 uses 9 modes for intra 4x4 and 4 modes for intra 16x16. In this paper, we propose an efficient uniform architecture for all of the 4x4 intra directional modes. This architecture offers an important gain in case of treatment time compared to the literature. Our proposed architecture is designed using VHDL language and implemented with FPGA and TSMC 0.18 mu m CMOS technologies.