Abstract
Three-dimensional Networks on chip 3D-NoCs represent a new generation of communication structure that enhances the performance and overcomes the limitations of two-dimensional NoCs. They offer, by replacing long interconnects by much shorter high-speed vertical links called Through-Silicon-Vias TSVs, fast and power efficient inter-core communication. However, vertical TSVs links bring several problems due to its large area footprint and increased manufacturing cost. In this context, we propose a new 3D-mesh NoC architecture based on shared TSVs and serialized data. This architecture is constructed using 2D and 3D routers. In this paper, we describe the design and implementation of the 2D router that ensures the intra-layer communication. It is characterized by its simple virtual channel allocation scheme that allows enhancing its area and power consumption characteristics.