Abstract
The low-power techniques are essential part of VLSI design due to continuing increase in clock frequency and complexity of chip. The synchronous circuit operates at highest clock frequency. These circuits drive a large load because it has to reach many sequential elements throughout the chip. Thus, clock signals have been a great source of power dissipation because of high frequency and load. Since, clock signals are used for synchronization, they does not carry any information and certainly doesn't perform any computation. Therefore, disabling the clock signal in inactive portions of the circuit is a useful approach for power dissipation reduction. So, by using clock gating we can save power by reducing unnecessary clock activities inside the gated module. In this chapter, we will review some of the techniques available for clock gating. The chapter also presents Register-Transfer Level(RTL) model in Verilog language. Along with RTL model we have also analyzed the behaviors of clock gating technique using waveform.