Abstract
Conference Title: 2017 IEEE 60th International Midwest Symposium on Circuits and Systems (MWSCAS) Conference Start Date: 2017, Aug. 6 Conference End Date: 2017, Aug. 9 Conference Location: Boston, MA, USA Recently, researchers are targeting low-power consumption, and integrating more blocks on-chip. This paper proposes a 1GS/s 6-bit time-based analog-to-digital converter (T-ADC) for front-end receivers. This T-ADC eliminates the preprocessing analog blocks, and reduces power consumption by removing the power-hungry sample and hold circuit. A prototype of the proposed T-ADC is implemented in 65nm CMOS technology, where it consumes 1 mW and achieves a maximum SNDR of 35.5 dB with sampling rate 1 GHZ that corresponds to a Figure of Merit (FoM) of 20.62 fJ/step.