Abstract
Analog-to-Digital Converters (ADCs) are essential blocks in digital signal processing (DSP) systems, software defined radio receivers (SDRs), and portable data acquisition systems. This paper introduces an 8-bit Time-based Analog to Digital Converter (T-ADC). This T-ADC utilizes an inherited sample and hold required to eliminate the dedicated power hungry sample and hold circuit. Moreover, a new design methodology for increasing the input dynamic range as well as improving the circuit sensitivity is implemented. A prototype of the proposed T-ADC is implemented in TSMC 65nm CMOS technology. This T-ADC consumes 1.9 mW, and achieves a maximum SNDR of 49.66 dB with sampling rate of 200 MS/s. Moreover, comparing the area proportion of the analog and digital parts of the T-ADC circuit reveals that one of the main advantages of the T-ADC over the conventional ADCs is that the digital part dominates the design (i.e., the digital part occupies about 98% of the whole proposed T-ADC).