A Class of Low Power Error Compensation Iterative Decoders

Amr M. A. Hussien; Muhammad S. Khairy; Amin Khajeh; Ahmed M. Eltawil; Fadi J. Kurdahi; IEEE

doi:10.1109/GLOCOM.2011.6134075

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Conference proceeding

A Class of Low Power Error Compensation Iterative Decoders

Amr M. A. Hussien, Muhammad S. Khairy, Amin Khajeh, Ahmed M. Eltawil, Fadi J. Kurdahi and IEEE

2011 IEEE GLOBAL TELECOMMUNICATIONS CONFERENCE (GLOBECOM 2011), pp.1-6

IEEE Global Telecommunications Conference (Globecom)

01/12/2011

DOI: https://doi.org/10.1109/GLOCOM.2011.6134075

Abstract

Engineering

Engineering, Electrical & Electronic

Science & Technology

Technology

Telecommunications

Recent power reduction techniques aggressively modulate the supply voltage of embedded buffering memories allowing acceptable hardware errors to flow through the processing chain. In this paper, we introduce a class of modified Turbo and LDPC decoders that provide significant improvements over standard decoders in the presence of hardware noise. Simulation results show a consistent improvement in the BER performance of the modified decoders across all SNRs with very small area and power overheads as compared to the conventional decoders.

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Details

Title: A Class of Low Power Error Compensation Iterative Decoders
Creators - without role: Amr M. A. Hussien - University of California, Irvine
Muhammad S. Khairy - University of California, Irvine
Amin Khajeh - University of California, Irvine
Ahmed M. Eltawil - University of California, Irvine
Fadi J. Kurdahi - University of California, Irvine
IEEE
Publication Details: 2011 IEEE GLOBAL TELECOMMUNICATIONS CONFERENCE (GLOBECOM 2011), pp.1-6
Series: IEEE Global Telecommunications Conference (Globecom)
Publisher: IEEE
Number of pages: 6
Identifiers: 9941454708331
Academic Unit: King Abdullah University of Science & Technology
Language: English
Resource Type: Conference proceeding