A High Speed Dynamic StrongARM Latch Comparator

Mohammed Al-Qadasi; Abdullah Alshehri; Abdullah S Almansouri; Talal Al-Attar; Hossein Fariborzi

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A High Speed Dynamic StrongARM Latch Comparator

Mohammed Al-Qadasi, Abdullah Alshehri, Abdullah S Almansouri, Talal Al-Attar and Hossein Fariborzi

The Institute of Electrical and Electronics Engineers, Inc. (IEEE) Conference Proceedings, p.540

01/01/2018

Abstract

CMOS

Energy consumption

High speed

Conference Title: 2018 IEEE 61st International Midwest Symposium on Circuits and Systems (MWSCAS) Conference Start Date: 2018, Aug. 5 Conference End Date: 2018, Aug. 8 Conference Location: Windsor, ON, Canada In this paper, a new design has been proposed for a high speed, low power StrongARM latch in 65nm CMOS technology. Latching speed improvements of 18% and 16% have been achieved in comparison to the conventional [4] and improved StrongARM [5], respectively, while the energy consumption has also been reduced.

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Title: A High Speed Dynamic StrongARM Latch Comparator
Creators - without role: Mohammed Al-Qadasi
Abdullah Alshehri
Abdullah S Almansouri
Talal Al-Attar
Hossein Fariborzi
Publication Details: The Institute of Electrical and Electronics Engineers, Inc. (IEEE) Conference Proceedings, p.540
Publisher: The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Identifiers: 9933340408331
Academic Unit: University of Jeddah; King Abdullah University of Science & Technology; Imam Abdulrahman Bin Faisal University
Language: English
Resource Type: Conference proceeding