Abstract
In this paper, a new architecture of a fully integrated low-dropout voltage regulator (LDO) is presented. It is composed of hybrid architecture of NMOS/PMOS power transistors to relax stability requirements and enhance the transient response of the system. The LDO is designed in UMC 130 nm CMOS technology and is capable of producing a stable output voltage of 1.1 V from 1.3 V single supply with recovery settling time congruent to 500 nsec. The LDO can supply current from 10 mu A to 100 mA consuming quiescent current of 23.7 mu A and 83.5 mu A, respectively. The performance of the proposed technique is compared with other reported techniques and gives a better performance. It can support load capacitance from 0-50 pF with phase margin that increases from 47 degrees at low load (10 mu A) to 80 degrees at high load (100 mA) and power supply rejection ratio (PSRR) less than -9 dB up to 1 MHz.