Abstract
Justified and complete verification for hardware designs is a critical step as industrial hardware designs becomes more and more complex. Moreover, one of the most important aspects of verification is coverage which monitors during simulation which design specification, features and also RTL code area is being covered. Following how important coverage is, most hardware verification tools provide different metrics for measuring coverage. Code coverage one of the most used metrics in hardware and even software simulation is responsible for checking which blocks of code is being exercised. However, as tools becoming more and more complex and provide large amount of features sometimes it becomes harder for quality assurance in tool testing to monitor and track the code coverage unit functionality in their tool. Also, some tools may not provide a mean to measure code coverage at all. This paper presents a novel method based on SystemVerilog assertions (SVA) to measure code coverage for hardware designs, justified and tested with a novel tool that can help QA engineers in debugging their code coverage units. Additionally, this tool can act as a standalone tool for measuring code coverage if the simulator does not naturally support it.