A Reusable Hybrid RISC Processor with Programmable Instruction Set

Hajer Najjar; Riad Bourguiba; Jaouhar Mouine

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A Reusable Hybrid RISC Processor with Programmable Instruction Set

Hajer Najjar, Riad Bourguiba and Jaouhar Mouine

The Institute of Electrical and Electronics Engineers, Inc. (IEEE) Conference Proceedings, p.1028

01/01/2018

Abstract

Central processing units

CPUs

Embedded systems

Instruction sets (computers)

Microprocessors

Power consumption

RISC

Conference Title: 2018 15th International Multi-Conference on Systems, Signals & Devices (SSD) Conference Start Date: 2018, March 19 Conference End Date: 2018, March 22 Conference Location: Yassmine Hammamet, Tunisia Embedded systems face several area and power consumption constraints in addition to the real-time challenges. This promotes the use of hard-core processors. However, their rigid instruction sets make them unsuitable for some applications. In this paper we propose a new processor design which adds the programmable aspect to a hardwired processor architecture, so that the reuse possibilities are increased.

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Title: A Reusable Hybrid RISC Processor with Programmable Instruction Set
Creators - without role: Hajer Najjar
Riad Bourguiba
Jaouhar Mouine
Publication Details: The Institute of Electrical and Electronics Engineers, Inc. (IEEE) Conference Proceedings, p.1028
Publisher: The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Identifiers: 9925680208331
Academic Unit: Prince Sattam Bin Abdulaziz University
Language: English
Resource Type: Conference proceeding