Abstract
Conference Title: 2018 14th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT) Conference Start Date: 2018, Oct. 31 Conference End Date: 2018, Nov. 3 Conference Location: Qingdao, China Ignoring some cells overlaps, the common objective of very large scale integration (VLSI) global placement problem is to minimize the total half-perimeter wirelength (IIPWL). Due to the non-differentiability of HPWL, the differentiable log-sum- exponential (LSK) wirelength model has been widely used to approximate IIPWL. In order to overcome the disadvantage of fixed parameter value in LSK, a self-adaptive LSK wirelength model has been presented in this paper. In each iteration of cells diffusion, the proposed wirelength model is dynamically updated according to the overflow of the circuit, and then a self-adaptive wirelength based nonlinear solver is used to solve the placement problem. Compared with a state-of-the-art LSE based placer, the experimental results show that our wirelength model not only can improve the solution quality, but also can reduce the runtime.