Abstract
This paper presents a single, scalable, unified statistical model that accurately reflects the impact of random embedded memory failures due to power management policies on the overall performance of a communication system. The proposed framework enables system designers to efficiently and accurately determine the effectiveness of novel power management techniques and algorithms that are designed to manage both hardware failure and communication channel noise, without the added cost of lengthy system simulations that are inherently limited and suffer from lack of scalability. Furthermore, the proposed framework facilitates performing both cross layer and intra layer tradeoffs where the faulty hardware can be treated as error-free hardware thus creating a much richer design space of power, performance and reliability.