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A clock gating design for high speed treatment and optimized power of image processing circuit
Conference proceeding

A clock gating design for high speed treatment and optimized power of image processing circuit

Siwar Ben Haj Hassine, Bouraoui Ouni, IEEE and Siwar Ben Haj Hassine
2016 17th International Conference on Sciences and Techniques of Automatic Control and Computer Engineering (STA), pp.123-126
12/2016
DOI: https://doi.org/10.1109/STA.2016.7952032

Abstract

Algorithm design and analysis clock gating Clocks digital circuit dynamic power Field programmable gate arrays high speed treatment Image processing image processing circuit Multiplexing Power demand Time factors
The recent rise of image processing circuits all along with the persistent quest for higher levels of performance have enormously contributed to the need of creating more efficient types of image processing circuit. For that, we have proposed a new design that offers us not only a less consuming circuit but also a faster one. Our new design has been tested and has given an interesting gain in power as well as in response time compared to classical one.

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