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A fixed delay infinite-bit split adder architecture and its application in real-time image processing
Conference proceeding

A fixed delay infinite-bit split adder architecture and its application in real-time image processing

Amjad Fuad Hajjar and IEEE
2006 INTERNATIONAL CONFERENCE ON MICROELECTRONICS, pp.194-197
01/01/2007

Abstract

Engineering Engineering, Electrical & Electronic Nanoscience & Nanotechnology Science & Technology Science & Technology - Other Topics Technology
A fixed delay split adder is presented. The adder breaks the total addition into sum and reminder with an expected reminder percentage of about 0.33% of the total sum. The adder is capable of producing the outputs in 6 gate delays regardless of the inputs bit-size. The proposed adder is applied to two realtime image processing applications and results showed very close matching to the perfect cases when ignoring the reminder.

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