Abstract
A low-power 900 MHz GSM frequency synthesizer (FS), with an on-chip LC-tuned voltage controlled oscillator (VCO) is presented. The synthesizer possesses several novel features that include a completely integrated structure, a low phase noise on-chip LC VCO, a low-power dual-modulus divider (DMD) in CML topology, a compensated charge pump with balanced switching, an on-chip third order loop filter and a proposed relatively easy to implement fractional accumulator based frequency synthesis technique. The complete synthesizer achieves in-bandphase noise characteristics better than -110 dBc/Hz at 100 kHz offset. The channel switching time is less than 500 /spl mu/s for a 25 MHz frequency transition. The proposed architecture has been realized using the 0.5 /spl mu/m AMI C5N technology. The complete integrated synthesizer occupies less than 1500 x 700 /spl mu/m/sup 2/ of die real estate with 22 mW power dissipation.