A new approach for real-time histogram equalization using FPGA

A.M. Alsuwailem; S.A. Alshebeili; IEEE

doi:10.1109/ISPACS.2005.1595430

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A new approach for real-time histogram equalization using FPGA

A.M. Alsuwailem, S.A. Alshebeili and IEEE

2005 International Symposium on Intelligent Signal Processing and Communication Systems, Vol.2005, pp.397-400

2005

DOI: https://doi.org/10.1109/ISPACS.2005.1595430

Abstract

Clocks

Concurrent computing

Costs

Counting circuits

Decoding

Field programmable gate arrays

Frequency

Hardware

Histograms

Statistics

This paper presents a novel design for real-time histogram equalization based on field programmable gate arrays (FPGAs). The design is implemented using non-conventional schemes to compute the histogram statistics and equalization in parallel. Counters are used in conjunction with a dedicated decoder specially designed for this purpose. The hardware is fast, simple, and flexible with reasonable development cost. The proposed system is implemented using Stratix II family chip type EP2S15F484C3. The maximum clock frequency can reach up to 250 MHz. In this case, the total time required to perform histogram equalization for an image of size 256 /spl times/ 256 is 0.262 ms.

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Title: A new approach for real-time histogram equalization using FPGA
Creators - without role: A.M. Alsuwailem - King Saud University
S.A. Alshebeili - King Saud University
IEEE
Publication Details: 2005 International Symposium on Intelligent Signal Processing and Communication Systems, Vol.2005, pp.397-400
Publisher: IEEE
Identifiers: 9952403408331
Academic Unit: King Saud University
Language: English
Resource Type: Conference proceeding