Abstract
A background calibration technique for gated-oscillator-based CDR/PLL is presented. This digital approach eliminates the frequency offset between the gated oscillator and the input data/reference clock to reduce the BER or output jitter. A 2.5Gb/s CDR based on this technique is designed without any local reference clock. It demonstrates error-free operation for a 2 31 -1 PRBS and tolerates more than 253 consecutive identical digits (CIDs). It also passes OC-48 jitter tolerance mask with sufficient margin.