Abstract
Conference Title: 2017 IEEE Applied Power Electronics Conference and Exposition (APEC) Conference Start Date: 2017, March 26 Conference End Date: 2017, March 30 Conference Location: Tampa, FL, USA Dynamic Voltage Scaling (DVS) has been shown to yield dramatic power savings in modern FPGAs. Because each user-specific hardware design has unique critical paths, the hardware reconfigurability of FPGAs renders the implementation of DVS much more challenging compared to CPUs. A promising FPGA DVS scheme relies on a two-step, offline self-characterization of the minimum supply voltage of the critical paths versus frequency and temperature. It does not, however, account for the resistive voltage drops in the power distribution network during regular operation. As a result, voltage guard-bands are necessary, reducing the power savings. In this paper, a self-calibration method is demonstrated to directly measure the on-chip voltage using a calibrated Delay-Line ADC (DL-ADC). The temperature dependent resistance between the dc-dc converter feedback point and the on-chip critical path is accurately extracted and used in regular DVS mode to compensate the voltage drop according to the load current. The new DVS scheme is demonstrated on an Altera Cyclone IV 60-nm FPGA with a digitally controlled dc-dc converter.