Abstract
This paper reports on a scalable and simple gate-first integration option for manufacturing the high-k/metal gate CMOS transistors targeting sub-32 nm LSTP applications: V t < plusmn 0.45 V (at L g = 60 nm) at EOT les 1.4 nm, with 10 5 times J g reduction compared to SiO 2 . This scheme integrates several simplifications and improvements for the first time: single metal gate material, single channel material, dual selective LaO x / AlO x cap removal without lithographic overlay tolerances issues and optimized HfSiON for LSTP leakage targets.