A technique for fast calculations of capacitance matrices of interconnect structures

V. Veremey; R. Mittra; IEEE

doi:10.1109/EPEP.1997.634081

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Conference proceeding

A technique for fast calculations of capacitance matrices of interconnect structures

V. Veremey, R. Mittra and IEEE

Electrical Performance of Electronic Packaging, pp.244-247

1997

DOI: https://doi.org/10.1109/EPEP.1997.634081

Abstract

Boundary element methods

Capacitance

Circuits

Delay estimation

Dielectrics

Finite difference methods

Packaging

Parameter extraction

Time domain analysis

A finite difference (FD) method for rapid and accurate evaluation of capacitance matrices of interconnect configurations is described. Novel techniques for the truncation of FD mesh, that significantly reduce the CPU time, are presented.

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Details

Title: A technique for fast calculations of capacitance matrices of interconnect structures
Creators - without role: V. Veremey - Pennsylvania State University
R. Mittra
IEEE
Publication Details: Electrical Performance of Electronic Packaging, pp.244-247
Publisher: IEEE
Identifiers: 9935931508331
Academic Unit: King Abdulaziz University
Language: English
Resource Type: Conference proceeding