Abstract
This paper presents a detailed digital design for the Random Spray Retinex (RSR) algorithm's main functionality. The proposed hardware architecture supports parallel computing and provides an efficient design in terms of speed, area, and power consumption compared to traditional designs. The implementation results show that the proposed parallel Application Specific Integrated Circuit (ASIC) design is highly efficient in reducing the computational complexity resulting from the data-intensive algorithm while greatly accelerating the RSR algorithm. The proposed method is seen as a step toward a low-complexity, real-time hardware architecture for the popular retinex algorithm used for image enhancement. Lastly, this architecture was implemented using standard ASIC design flow with 22nm foundry technology; it occupied an area of 430.24 \mu m^{2} and consumed a total power of 66.6 \mu W, for 4 points per spray, making it very suitable for integrated System on Chips (SoC). Furthermore, the design can be scaled to a higher number of points per spray.