Abstract
Power consumption poses a challenge issue in Wireless Sensor Networks as the sensor node is power-constrained. Since Wireless communication is among the most energy expensive tasks, many power efficient transmission strategies are reported in the literature. However, most of them are purely software-based implemented. Since relaying algorithms are intensive-computing tasks, a purely software-based implementation is not the wise choice. This work comes to propose an alternative choice for implementing our earlier proposed relaying algorithm, which is a HW/SW implementation. To do so, we have identified the greedy CPU time and energy consuming tasks and implemented their dedicated hardware accelerators. We prototype our work using an FPGA board. Design details and interfacing of the different accelerators show important time execution and power consumption reduction of our algorithm.