Abstract
Multiple-input multiple-output (MIMO) has emerged as a generic technique that promises to be a strong contender for 4G wireless systems. Even with extensive research on the design of transmission and reception algorithms, little is known about the complexity of hardware implementation. This paper proposes an efficient hardware prototype for MIMO decoding that utilizes the resources of the device by adopting the technique of parallelism. The decoder is designed and implemented as a part of MIMO testbed on a Xilinx Virtex (TM)-4 XC4VLX60 Field Programmable Gate Arrays (FPGA) device. In this paper, a comprehensive explanation of the complete design process is provided, including an illustration of the tools used in its development. The decoder is developed based on modular design which simplifies system design, eases hardware update and facilitates testing the various modules in an independent manner.