Abstract
Conference Title: 2018 18th Mediterranean Microwave Symposium (MMS) Conference Start Date: 2018, Oct. 31 Conference End Date: 2018, Nov. 2 Conference Location: Istanbul, Turkey This This paper proposes SiGe heterojunction Bipolar cascoded with a mosFET(BiFET) LNA with no inductor, which is capable of concurrently operating at 60 GHz and 120 GHz bands. The LNA utilizes a simple 03-transmission lines TLs impedance transformer to match input impedance $\mathbf{Z}_{\mathbf{I}\mathbf{N}}$ to the optimum noise resistance $\mathbf{R}_{\mathbf{ORT}}$ for minimum noise and $\mathbf{Z}_{\mathbf{OUT}}$ to $\pmb{ 50\Omega}$ at the output for power matching at both the bands. In the LNA circuit SiGe HBT $(\mathbf{Q}_{\pmb{1}})$ is used in the 1st stage and MOSFET $(\mathbf{M}_{\pmb{1}})$ in the 2ndstage to utilize best of the SiGe HBT (i.e. low noise) and MOSFET (i.e. high linearity) with inter-stage transmission line TL3 to compensate for signal loss at high frequency (More specifically @120GHz). The transmission line used at the gate $\mathbf{TL}_{\pmb{4}}$ of $\mathbf{M}_{\pmb{1}}$ in the proposed LNA is used to achieve power gain peaking. By representing $\mathbf{TL}_{\pmb{3}}$ and $\mathbf{TL}_{\pmb{4}}$ with corresponding lumped inductors $\mathbf{L}_{\pmb{3}}$ and $\mathbf{L}_{\pmb{4}}$, respectively in small-signal model of the LNA, signal loss due to parasitic capacitance $\mathbf{C}_{\mathbf{P}}$ at the collector node of $\mathbf{Q}_{\pmb{1}}$ at high frequency is analytically analyzed. Theoretically, predicted S-parameters of the LNA using small-signal model were found to overestimate the simulation results due to its simplified formulation. The Keysight ADS EM co-simulated transfer gain $\mathbf{S}_{\pmb{21}}=\pmb{18.6}\mathbf{dB}$ @60GHz and 18.2dB @120GHz, respectively has been realized. The proposed LNA provides 3-dB bandwidth of $\pmb{> 6.0}\mathbf{GHz}$ at both the bands and $\mathbf{NF}=\pmb{5.5}\mathbf{dB}$ and 8.6 dB @60GHz and 120GHz, respectively with input third-order intercept $\mathbf{IIP}_{\pmb{3}} > +\pmb{4.0}\mathbf{dBm}$ at both the bands and consume dc power of 8.64mW. The proposed LNA layout occupies a chip area of $\pmb{0.6}\mathbf{mm}^{\pmb{2}}$. A state-of-art new Figure-of-Merit (FoM) accounting chip area as well as involving key performances like $\mathbf{S}_{\pmb{21}}$, noise factor F, $\mathbf{IIP}_{\pmb{3}}$ and $\mathbf{P}_{\mathbf{DC}}$ was found to be significantly higher for the proposed SiGe BiCMOS LNA than previously reported experimental results of LNA using the same technology.