Abstract
An ultra-low power voltage-to-time converter (VTC) circuit is proposed. The VTC circuit is compatible with wide range of applications (i.e. sensors, integrated DC-DC voltage converters) especially for time-based analog-to-digital converters (T-ADCs). In TADCs, the input voltage signal is first converted into a delay pulse using the VTC circuit, then this delay signal is converted into a digital code through time-to-digital converter (TDC). The main advantages of the T-ADC are that it: 1) eliminates the need for pre-amplifier stages, 2) operates at low supply voltage, and 3) supports low-speed applications as well as high-speed applications. In this paper, two VTC architectures are presented: a single ended architecture, and a fully differential architecture. The core VTC architecture uses a modified current starved inverter biased in subthreshold to maintain low-power consumption level. A prototype of the proposed VTC is implemented in 130nm CMOS technology, it exhibits a nonlinearity of 1 % per 150mV for single-ended architecture, while exhibits nonlinearity of +/- 0.4 % per 240-mV for the fully differential one.