Sign in
An adaptive serial-parallel CAM architecture for low-power cache blocks
Conference proceeding

An adaptive serial-parallel CAM architecture for low-power cache blocks

A. Efthymiou and J.D. Garside
Proceedings of the International Symposium on Low Power Electronics and Design, pp.136-141
2002

Abstract

CADCAM Computer aided manufacturing Computer architecture Computer science Energy consumption Permission Random access memory Read-write memory Silicon Very large scale integration

Metrics

1 Record Views

Details