Abstract
Due to its potential greatly accelerate a wide variety of applications and many properties such as reconfigurability, adaptation and reprogramability, Field Programmable Gate Arrays (FPGAs) become new tool and target primitive for implementing the FPGA-based digital systems. FPGA devices become increasingly adopted not only for the design of digital systems, but also for replacement of traditional computing devices. Time delay is an essential element that determines the performance of the FPGA-based digital systems. The paper presents an overview of different approaches used for FPGA time delay modeling and evaluation. The paper introduces the basic (delta and constant) time delay modeling, asymmetric modeling, load sensitive modeling, ASIC cell modeling and Configurable Logic Block (CLB) time delay modeling.