Abstract
A low power, short duration analog chirp generator is designed for IoT applications by cascading All-Pass Filter (APF) sections, as an alternative to existing complex and bulky chirp generator modules. First, a single section APF is designed. It is further modified to build a 40-section cascaded configuration to generate the desired chirp waveform. Trade-offs in BW and T-chirp with varying number of cascaded Sections (N) and capacitance (C-buf) are further analyzed.The circuit is designed in a 22nm FDSOI process and is stable with temperature variations. Post-layout simulations indicate a BW of 140 MHz and T-chirp of 90ns. Total chip area is 0.5mm x 0.5mm.The circuit is stable with temperature variations from 0 to 100 degrees.