Abstract
The objective of the hArtes (Holistic Approach to Reconfigurable real Time Embedded Systems) is to provide a toot set that facilitates the management of entire design flow Despite of its improved design productivity, the two bottleneck are: (1) capturing initial application specifications in the specified graphical tool and (2) Cycle accurate performance estimation in design space exploration.
We propose: (1) a transformation methodology for converting reference sequential C code to data-flow specifications and (2) a design space exploration framework based on cycle accurate performance estimation. The proposed transformation methodology is based on functions re-organization and variables definitions. The proposed design space exploration framework consists of two design loops: computational architecture selection loop and communication architecture selection loop. Before entering into these loops, it is critical to estimate the performance of application function blocks. We propose a performance estimation methodology by performing simulations at CABA (Cycle Accurate Bit Accurate) level. Instead of simulating the entire application, each function block is instrumented and executed oil the target simulation platform and the resulting information is stored in a performance estimation library.
Experimentation with H.264 video encoding application proves the viability of the proposed transformation methodology. Validation and performance evaluations for performance estimation technique are done by extending the SoCLib library of simulation models.