Abstract
Hardware design abstraction has significantly favoured productivity in the recent years. The clock is known to be the beating heart of every digital design which coordinates the communications and computations. Due to the critical role of this signal a proper management of it is essential. Newly emerged high-level synthesis and hardware construction tools either reflect this responsibility to the designer at high level or make some general assumptions based upon critical paths which may also require the designer to re-architecture the design when the assumptions encounter failure. This can exert a profound impact on designer's productivity. We propose the AutoCLK technique to handle the clock automatically which calls for specific properties, such as 'slack elasticity' and distributed control flow, in the target architecture. Our experiments demonstrate that both low-level and high-level factors have to be taken into account for efficient clock management.