Abstract
Conference Title: 2014 IEEE International Symposium on Circuits and Systems (ISCAS) Conference Start Date: 2014, June 1 Conference End Date: 2014, June 5 Conference Location: Melbourne VIC, Australia Extracting data paths in large-scale register-transfer level designs has important usage in automatic verification of synchronous circuits and synthesis of asynchronous circuits. Current tools rely on users to provide the data/control partition or use state-space analyses to extract data paths. Due to the explosion of state-space, the latter method can be used in only small designs. To resolve this problem, a graphic search and trim method, which can extract data paths in large scale designs, is presented. A design is first translated into a graphic representation, namely a signal-level data flow graph (DFG), to reveal the connections between signals. By estimating the types (control or data) of these connections, a linear search algorithm can then remove all control-related signals in the graph, which effectively produces a DFG with pure data paths. Results show that this method extracts data paths of large scale designs in seconds. [PUBLICATION ABSTRACT]