Abstract
Conference Title: 2018 15th International Multi-Conference on Systems, Signals & Devices (SSD) Conference Start Date: 2018, March 19 Conference End Date: 2018, March 22 Conference Location: Yassmine Hammamet, Tunisia Global interconnects are the main performance bottleneck for nowadays complex Systems on Chip. The Network on chip paradigm is a new interconnection solution outperforming the bus based on chip interconnects. Many studies focused on the improvement of NoC performances in terms of latency, throughput and power consumption. In this paper, a new switch architecture addressing the problem of buffers underutilization is proposed. It enables the exploitation of traffic patterns orientation by adaptively sharing free virtual channels among different input ports. This switch improves the latency and throughput performances.