Abstract
Conference Title: 2018 IEEE 61st International Midwest Symposium on Circuits and Systems (MWSCAS) Conference Start Date: 2018, Aug. 5 Conference End Date: 2018, Aug. 8 Conference Location: Windsor, ON, Canada This paper deals with CMOS fractional-order inductance $(FoL)$ simulator design and its utilization in $2.75^{th}-$ order Colpitts oscillator providing high frequency of oscillation. The proposed floatingFoL is composed of two unity-gain current followers $(CF \pm s)$, two inverting voltage buffers, a transconductor, and a fractional-order capacitor $(FoC)$ of order 0.75, while the input intrinsic resistance of $CF \pm$ is used as design parameter instead of passive resistor. The resulting equivalent inductance value of theFoL can be adjusted via order of FoC, which was emulated via 5th-order Foster II RC network and values optimized using modified least squares quadratic method. In frequency range 138 $kHz-2.45$ MHz theL r shows ± 5 degree phase angle deviation. Theoretical results are verified by SPICE simulations using TSMC 0.18 $\mu m$ leve1-7 LO EPI SCN018 CMOS process parameters with $\pm 1V$ supply voltages.