Abstract
The use of deep sub-micron CMOS processes presents several daunting challenges to the RF designers. The latest CMOS technologies, optimized for parameters suited to digital designs only, are forcing the analog and mixed-signal designers to make multi-dimensional trade-offs. In general, the lack of adequate analog device characterization and inaccurate SPICE models mandate several expensive additional design and fabrication iterations before arriving at an acceptable solution. Sometimes, the task is further complicated by the difficulty in even making reliable lab measurements due to accuracy issues caused by probing noise, minuscule device sizing, dynamic effects and loading. This paper summarizes the harmonic characterization techniques used to estimate the mismatches in the minimal size inversion-type CMOS varactors in a digitally controlled oscillator (DCO). The DCO is a centerpiece of the first ever all-digital phase locked loop (ADPLL) fabricated in 90 nm digital CMOS that meets the challenging GSM performance specifications. Simulation as well as lab measurements confirm that the tracking bank varactors have a better than 5.5% mismatch, thus contributing to the excellent modulation performance.