Cross layer error exploitation for aggressive voltage scaling

Amin Khajeh Djahromi; Ahmed M. Eltawil; Fadi J. Kurdahi; Rouwaida Kanj

doi:10.1109/ISQED.2007.53

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Conference proceeding

Cross layer error exploitation for aggressive voltage scaling

Amin Khajeh Djahromi, Ahmed M. Eltawil, Fadi J. Kurdahi and Rouwaida Kanj

ISQED 2007: PROCEEDINGS OF THE EIGHTH INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN, pp.192-197

01/01/2007

DOI: https://doi.org/10.1109/ISQED.2007.53

Abstract

Engineering

Engineering, Electrical & Electronic

Science & Technology

Technology

This paper shows that by co-designing circuits and systems, considerable power savings are possible if the inherent data redundancy of candidate systems such as wireless is used to compensate for hardware failures. A comprehensive study of 6T SRAM failure modes is presented. The generated statistics are used to quantify a power savings of up to 17.5% for a case study of a 32 nm CMOS 3GPP WCDMA modem.

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Title: Cross layer error exploitation for aggressive voltage scaling
Creators - without role: Amin Khajeh Djahromi - University of California, Irvine
Ahmed M. Eltawil - University of California, Irvine
Fadi J. Kurdahi - University of California, Irvine
Rouwaida Kanj - IBM Research - Austin
Publication Details: ISQED 2007: PROCEEDINGS OF THE EIGHTH INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN, pp.192-197
Publisher: IEEE
Number of pages: 2
Identifiers: 9942611408331
Academic Unit: King Abdullah University of Science & Technology
Language: English
Resource Type: Conference proceeding