Abstract
This paper seeks to study the contributing factors to current mismatch among parallelled SiC power modules, including the gate driver circuits, and the impedance of the bus barsm, the load connection and the load impedance. Compared with using silicon power devices, the effect of impedance asymmetry and inductive coupling is more pronounced with SiC power modules due to significantly lower on-resistance, lower load inductance and higher steady state di/dt. It is also revealed that nanosecond-level mismatch in the gate driver circuits can lead to significant dynamic current mismatch. Hardware tests and detailed simulations are carried out to explore these effects, and finally achieving 2.41% mismatch in dynamic switching energy and minimal mismatch in the steady state current sharing.