Design and FPGA implementation of ternary hardware IP core for square root function

Siwar Ben Haj Hassine; Mehdi Jemai; Bouraoui Ouni

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Design and FPGA implementation of ternary hardware IP core for square root function

Siwar Ben Haj Hassine, Mehdi Jemai and Bouraoui Ouni

The Institute of Electrical and Electronics Engineers, Inc. (IEEE) Conference Proceedings, p.1

01/01/2017

Abstract

Algorithms

Computer simulation

Field programmable gate arrays

Hardware

Power consumption

VHDL

Conference Title: 2017 International Conference on Engineering & MIS (ICEMIS) Conference Start Date: 2017, May 8 Conference End Date: 2017, May 10 Conference Location: Monastir, Tunisia This paper presents an algorithm of ternary hardware IP core and its implementation on FPGA. This IP core that solves the square root function is considered as the first developed algorithm that handles a complex ternary mathematical operation. The algorithm has been coded using VHDL language, simulated and implemented using Xilinx Spartan 3 FPGA board. Design results have proven not only accurate results that our IP code provides (error equals 0) but also its good performance in terms of latency, FPGA resources and power consumption.

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Title: Design and FPGA implementation of ternary hardware IP core for square root function
Creators - without role: Siwar Ben Haj Hassine
Mehdi Jemai
Bouraoui Ouni
Publication Details: The Institute of Electrical and Electronics Engineers, Inc. (IEEE) Conference Proceedings, p.1
Publisher: The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Identifiers: 9923495808331
Academic Unit: King Khalid University
Language: English
Resource Type: Conference proceeding