Abstract
Nowadays, the field of digital signal processing represents a bottleneck in computer systems design, because the applications used by computers are getting more complicated thus need more resources. FPGAs have been placed as parts on embedded systems to carry heavy loads out of the processors or microcontrollers. The main advantage of FPGAs is that they can do more than one job in parallel. The Discrete Cosine Transform (DCT) is often used in signal and image processing, especially lossy data compression, because it has a strong "energy compaction" property. The aim of this project is to solve the problem of implementing DCT algorithm on FPGA using Hardware Descriptive Languages (HDLs). The design will be optimized to decrease consumed logic cells and therefore provide maximum hardware utilization. The designed system was implemented and tested. The results were as expected; however some limitations were discovered and should be eliminated in the future.