Design and implementation of an new Built-In Self-Test boundary scan architecture

M.H. El-Mahlawy; E.A. El-Sehely; A.S. Ragab; S. Anas; ECE-CUFE

doi:10.1109/ICM.2003.238299

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Design and implementation of an new Built-In Self-Test boundary scan architecture

M.H. El-Mahlawy, E.A. El-Sehely, A.S. Ragab, S. Anas and ECE-CUFE

Proceedings of the 12th IEEE International Conference on Fuzzy Systems (Cat. No.03CH37442), Vol.2003-, pp.27-31

2003

DOI: https://doi.org/10.1109/ICM.2003.238299

Abstract

Automatic testing

Built-in self-test

Circuit testing

Field programmable gate arrays

Logic testing

Pins

Process control

Programmable logic arrays

Registers

System testing

The boundary scan (BS) technique offers a convenient alternative to physical probing. This paper presents new boundary scan architecture for Built-In Self-Test (BIST). The Boundary Scan Register (BSR) input cells have been configured to operate as a Test Pattern Generator (TPG) in the BIST mode. The BSR output cells have been configured to operate as a Multi-Input Shift Register (MISR) In the BIST mode. The Test Access Port Controller (TAPC) controls the BIST process. Instructions for BIST process are proposed. This configuration supports the BIST for both the Built-In Logic Block Observer (BILBO) register and the register transfer level. This design Implemented on the Field Programmable Gate Array (FPGA) Spartan X2C200 family.

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Title: Design and implementation of an new Built-In Self-Test boundary scan architecture
Creators - without role: M.H. El-Mahlawy
E.A. El-Sehely
A.S. Ragab
S. Anas
ECE-CUFE
Publication Details: Proceedings of the 12th IEEE International Conference on Fuzzy Systems (Cat. No.03CH37442), Vol.2003-, pp.27-31
Publisher: IEEE
Identifiers: 9951584008331
Academic Unit: King Saud University
Language: English
Resource Type: Conference proceeding