Design of High-Speed LVDS Data Communication Link Using FPGA

Shraddha Shukla; Jitendra P. Chaudhari; Rikin J. Nayak; Hiren K. Mewada

doi:10.1007/978-3-319-63645-0_1

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Design of High-Speed LVDS Data Communication Link Using FPGA

Conference proceeding

Peer reviewed

Design of High-Speed LVDS Data Communication Link Using FPGA

Shraddha Shukla, Jitendra P. Chaudhari, Rikin J. Nayak and Hiren K. Mewada

INFORMATION AND COMMUNICATION TECHNOLOGY FOR INTELLIGENT SYSTEMS (ICTIS 2017) - VOL 2, Vol.84, pp.1-9

Smart Innovation Systems and Technologies

01/01/2018

DOI: https://doi.org/10.1007/978-3-319-63645-0_1

Abstract

Computer Science

Computer Science, Artificial Intelligence

Science & Technology

Technology

This paper proposed the design and implementation of high speed communication link between two FPGAs using LVDS driver using 100 MHz clock. Initially Asynchronous and Synchronous communication are discussed and then synchronous communication is used for LVDS data communication. The speed of the communication is sensitive to the noise and sampling of the data at the receiver end. Therefore, the differential signal voltage level and sampling at the falling edge of clock are proposed in the design to maintain the high speed.

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Title: Design of High-Speed LVDS Data Communication Link Using FPGA
Creators - without role: Shraddha Shukla - Charotar University of Science and Technology
Jitendra P. Chaudhari - Charotar University of Science and Technology
Rikin J. Nayak - Charotar University of Science and Technology
Hiren K. Mewada - Charotar University of Science and Technology
Contributors - without role: S C Satapathy
A Joshi
Publication Details: INFORMATION AND COMMUNICATION TECHNOLOGY FOR INTELLIGENT SYSTEMS (ICTIS 2017) - VOL 2, Vol.84, pp.1-9
Series: Smart Innovation Systems and Technologies
Publisher: Springer Nature
Number of pages: 9
Identifiers: 9924848008331
Academic Unit: Prince Mohammad Bin Fahd University
Language: English
Resource Type: Conference proceeding