Abstract
This work introduces a novel design for a one bit full adder that has the advantages of high speed, low power consumption, and also a relatively low transistor count. The proposed full adder circuit is constructed from a 19 MOS transistors with the fact that at any given moment of operation time only few transistors are on. The circuit is simulated in 0.13 mu m CMOS technology. Simulation results illustrate that this full adder can work at 4 Gb/s with power consumption 4.8mW and acceptable power delay product.