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Dipole Model Explaining High-k/Metal Gate Threshold Voltage Tuning
Conference proceeding

Dipole Model Explaining High-k/Metal Gate Threshold Voltage Tuning

P. D. Kirsch, P. Sivasubramani, J. Huang, C. D. Young, C. S. Park, K. Freeman, M. M. Hussain, G. Bersuker, H. R. Harris, P. Majhi, …
ADVANCED GATE STACK, SOURCE/DRAIN, AND CHANNEL ENGINEERING FOR SI-BASED CMOS 5: NEW MATERIALS, PROCESSES, AND EQUIPMENT, Vol.19(1), pp.269-276
ECS Transactions
01/01/2009

Abstract

Electrochemistry Engineering Engineering, Electrical & Electronic Materials Science Materials Science, Coatings & Films Physical Sciences Physics Physics, Condensed Matter Science & Technology Technology

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