Abstract
We report on the promise of dual channel materials using FinFETs for high-performance CMOS for sub 22 nm technology node. We demonstrate pFinFETs with all SiGe channel formed by Germanium condensation onto a Silicon-On-Insulator carrier wafer (SiGeOI) followed by cMOS processing. The devices exhibit 3.6X hole mobility enhancement over Silicon (100) while allowing for V-TH control with single high-k and metal gate stack. These attributes taken together constitute a simple non-planar cMOS integration sequence with enhanced drive current for future high performance technology nodes.
Introduction: Multiple gate MOSFET architectures such as FinFETs are expected to be utilized beyond the 22nm node due to excellent SCE immunity [1]. Even so, conventional processing techniques for planar CMOS platforms to enhance device performance have not been widely reported for 3D MOSFETs due to processing difficulty or incompatibility [2]. Hence, there is a need for techniques to extend the utility of multi-gated devices beyond simple SCE control to provide technology for several nodes past 22nm. In this work, we simultaneously address the need for low V-TH without the use of metastable p-type band edge HK/MG stacks, SiGe hole mobility rivaling the best strain enhanced Silicon, and superior short channel effect suppression with dual gate device architecture.
Experimental: SOI (100) wafers were thinned to 10nm Si thickness prior to deposition of 70nm Si1-xGe0.2. Oxidation forced Germanium into the underlying SOI to produce a crystalline and homogeneous layer of SiGe on insulator. This technique can be applied selectively in pMOS regions to achieve dual channel materials on the same wafer [3]. Both Secondary Ion Mass Spectroscopy (SIMS) and electron energy loss spectroscopy (EELS) profiles verify the uniformity of the Germanium in the SiGe layer before and after fin formation (figs. 1,2). Active patterning produces fins with either {110}< 110 > or {100}< 100 > channel orientation and comparison of the crystalline lattice by Fourier transforms of TEM images from fins and the carrier wafer indicate that residual compressive strain (epsilon similar to.015) exists in the SiGe fin (fig 3). Because fin patterning reduces spatial dimension of the biaxial residual strain field, we expect an effective uniaxial strain along the fin direction resulting in enhanced hole mobility [4]. After HF preclean, Halfnium based high-k dielectric, midgap metal, and poly-Si depositions were etched to form the gate. Nitride spacer formation, Boron ion implantation, 1.5s 1070 degrees C spike activation anneal, and Ni salicide completed the front end processing with neutral stress contact etch stop layer (CESL), TEOS interlayer dielectric (ILD), Tungsten plugs, and Aluminum metallization completing device fabrication.
Results and Discussion: Figure 4 compares insertion points for incorporation of non-planar SiGe channels for hole mobility enhancement either by SiGe epitaxy around fully formed fins (SiGe shell) or Germanium condensation (SiGeOI) [5,4]. SiGeOI integration offers two crucial benefits compared to a SiGe shell option: 1) superior scaling pathway to maintain appropriate Lg to channel thickness ratio for SCE control and 2) removes difficulty of epi SiGe growth on Si (110) (fig.5) [7]. Controlled gate and junction leakage and excellent transfer characteristics indicate SiGeOI compatibility with conventional Si FinFET processing (fig.6). Large positive threshold voltage shift due to SiGe channel makes possible low pMOS V-TH alongside HK/MG tuned nMOS FinFET (fig.7) [8]. While figure 8 shows higher pMOs drive current, adjusting the Ge condensation process can tailor N/P performance for compatibility within existing or new cMOS circuitry. Device mobility extracted by split CV is given in figure 9. This high mobility compares well with simulation for fully strained Si1-xGe0.2 (110) indicating high quality channel and possibly some residual strain [5]. Accumulation leakage remains constant with de/creasing temperature indicating low junction defectivity in both SiGeOI and Si pFinFETs (fig 10). Room temperature stretch out sub-flatband and minor low temperature hysteresis was observed for the SiGeOI FinFET C-V characteristic indicating some defectivity in the gate dielectric interface (fig11). Peak mobility vs. temperature shown in figure 12 also shows steeper dependence for the SiGeOI fins case compared to reference Si or SiGe shell fins due a large number of either surface or bulk defects within the gate dielectric. Indeed, Jg-Tinv shown in figure 13 indicates more than 5A difference in the SiGe and Si at comparable leakage levels. These data imply a potential underestimation of inversion charge from C-V and therefore mobility. To further examine the dielectric-channel interface, we performed BTI on gated diode structures (fig.14). The change in "body" current for this type of test is directly proportional to Dit [9]. The IV curves depicting magnitude of Q(IT) trap charge generation indicates an interface trap density one order of magnitude larger in SiGe vs. the Si control (fig.15). Chemical oxide surface passivation and/or sacrificial oxidation of the SiGeOI fin is expected to circumvent these issues when using low Ge% films. Short gate length device characteristics are given in figures 16 and 17. We have used the R-TOT 1/beta technique to calculate R-S/D of the SiGeOI devices [10]. Both Si and SiGeOI devices show a minor R-S/D dependence on gate overdrive as expected from the underlap doping profile [11]. SiGeOI devices suffer an average penalty of similar to 30% higher R-S/D compared to Si devices due to unoptimized dopant profile (fig 18). The advantage of SiGe mobility can be further realized for short Lg devices provided that source-drain module optimization can achieve parity with Si R-S/D values.
Conclusion: We have demonstrated the utility of incorporating dual channel FinFET devices with a single HK/MG stack to simultaneously achieve low and symmetric VTH, hole mobility higher than conventional strained Si, and SCE suppression. The devices proved to be fully compatible with Si CMOS thermal budget highlighting the ease of manufacturing. Finally, optimization of gate preclean and dopant profile is expected to radically improve BTI characteristics, DIBL, SS, and R-S/D for sub 40nm Lg SiGe pFinFETs.