Efficient FPGA hardware implementation of secure hash function SHA-256/Blake-256

Fatma Kahri; Hassen Mestiri; Belgacem Bouallegue; Mohsen Machhout

doi:10.1109/SSD.2015.7348105

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Efficient FPGA hardware implementation of secure hash function SHA-256/Blake-256

Fatma Kahri, Hassen Mestiri, Belgacem Bouallegue and Mohsen Machhout

2015 IEEE 12th International Multi-Conference on Systems, Signals & Devices (SSD15), pp.1-5

01/03/2015

DOI: https://doi.org/10.1109/SSD.2015.7348105

Abstract

Blake-256

Clocks

Decision support systems

FPGA Implementation

Security

SHA-256

Throughput

Yttrium

Since the beginning of study of the Secure Hash function (SHA), it has been thoroughly studied by designers with the goal of reducing the area, frequency, and throughput of the hardware implementation of this cryptosystem. The Secure Hash function algorithm has become the default choice for security services in numerous applications. In this paper, we proposed a new design for the SHA-256 and Blake-256 functions. Moreover, the proposed design has been implemented on Xilinx Virtex-5 FPGA. Its area, frequency and throughput have been compared and it is shown that the proposed design achieve good performance in term of area, frequency and throughput.

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Details

Title: Efficient FPGA hardware implementation of secure hash function SHA-256/Blake-256
Creators - without role: Fatma Kahri - University of Monastir
Hassen Mestiri - University of Monastir
Belgacem Bouallegue - University of Monastir
Mohsen Machhout - University of Monastir
Publication Details: 2015 IEEE 12th International Multi-Conference on Systems, Signals & Devices (SSD15), pp.1-5
Publisher: IEEE
Identifiers: 9926355808331
Academic Unit: Prince Sattam Bin Abdulaziz University; King Khalid University
Language: English
Resource Type: Conference proceeding