Abstract
An energy-efficient 5Gb/s baseband (BB) transceiver for three-dimensional (3D) memory interconnect is introduced. The proposed transceiver exploits low power and high-speed output driver and through-silicon via (TSV), very short vertical interconnects, to improve I/O memory interface performance and power consumption. High-Frequency Structure Simulator (HFSS) is utilized to model 3D TSV interconnects and generate S-parameters. To validate the proposed architecture, the design is simulated in a 0.13 mu m CMOS processor. The outcomes reveal that the proposed architecture attains 5Gb/s/pin at 6.1mW and improves energy efficiency.