Abstract
This paper proposes a novel energy efficient architecture for computing Discrete wavelet transform (DWT) of an image using the Fractional wavelet filter (FrWF) approach. The proposed architecture needs to read only a single image line in memory at a time, which results in less memory requirement. The performance of the proposed architecture is compared with existing FrWF architecture by implementing both the architectures on same FPGA board. Experimental results demonstrate that for an image of dimension 512x512, the proposed architecture has 50% lower number of computational cycles, requires 80% less number of multipliers, and 47.34% lower energy consumption than the FrWF architecture. The lower hardware resource requirement, reduced power consumption and reduced energy consumption of the proposed architecture make it suitable for computing DWT of images over Wireless multimedia sensor networks/Internet of things.