Abstract
In this paper we propose an efficient technique for energy savings in DSM technology. The core of this method is based on low-voltage signaling over long on-chip interconnect with repeaters insertion to tolerate DSM noise and to achieve an acceptable delay. We elaborate a heuristic algorithm, called VIJIM, for repeaters insertion. VIJIM algorithm has been implemented to design a robust inverter chain for on-chip signaling using 0.25 mum, 2.5V, 6 metal layers CMOS process. An average of 70% of energy-saving has been achieved by reducing the supply voltage from 2.5V down to 1.5V.