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Enhanced performance and SRAM stability in FinFET with reduced process steps for source/drain doping
Conference proceeding

Enhanced performance and SRAM stability in FinFET with reduced process steps for source/drain doping

J. -W. Yang, H. R. Harris, M. M. Hussain, B. Sassman, H. -H. Tseng, R. Jammy and IEEE
2008 INTERNATIONAL SYMPOSIUM ON VLSI TECHNOLOGY, SYSTEMS AND APPLICATIONS (VLSI-TSA), PROCEEDINGS OF TECHNICAL PROGRAM, pp.20-21
01/01/2008
DOI: https://doi.org/10.1109/VTSA.2008.4530779

Abstract

Engineering Engineering, Electrical & Electronic Science & Technology Technology
Improved static noise margin in SRAM of 18% and decreased intrinsic inverter delay of 6% is demonstrated for the first time in double-gate CMOS finFET with gate-source/drain underlap doping. The excellent results are achieved by optimization of the spacer while simplifying the processing of source/drain region by skipping costly implants. Improved circuit and device performance with reduced processing steps make finFETs a more attractive option for 32nm technology node and beyond.

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