FPGA implementation for channel estimations based on Wiener LMS for DS-CDMA

M. Elnamaky; M. Ahmed-Ouameur; D. Massicotte; IEEE

doi:10.1109/SIPS.2005.1579940

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FPGA implementation for channel estimations based on Wiener LMS for DS-CDMA

M. Elnamaky, M. Ahmed-Ouameur, D. Massicotte and IEEE

IEEE Workshop on Signal Processing Systems Design and Implementation, 2005, Vol.2005, pp.618-622

2005

DOI: https://doi.org/10.1109/SIPS.2005.1579940

Abstract

Base stations

Channel estimation

Delay estimation

Field programmable gate arrays

Filters

Hardware

Least squares approximation

Maximum likelihood detection

Multiaccess communication

Smoothing methods

The estimation of channel delays along with their respective complex channel coefficients of different users constitutes the first stage in the detection process at the receiving base station in a DS-CDMA communication system. A multiuser steepest Wiener LMS (MS-WLMS) like structure algorithm along with smoothing/prediction filters to improve tracking quality is suggested. This paper presents a customized and fixed-point hardware parallel implementation of the proposed algorithm for WCDMA uplink transmission in third generation (3G) wireless system. Additional speedup in the execution time is achieved over the well known maximum likelihood channel estimation for DS-CDMA. It is also shown that our solution could achieve the real-time requirements of 3GPP standards applied in WCDMA systems.

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Title: FPGA implementation for channel estimations based on Wiener LMS for DS-CDMA
Creators - without role: M. Elnamaky - Université du Québec à Trois-Rivières
M. Ahmed-Ouameur - Université du Québec à Trois-Rivières
D. Massicotte - Université du Québec à Trois-Rivières
IEEE
Publication Details: IEEE Workshop on Signal Processing Systems Design and Implementation, 2005, Vol.2005, pp.618-622
Publisher: IEEE
Identifiers: 9952562608331
Academic Unit: King Saud University
Language: English
Resource Type: Conference proceeding